徹底解析~Benchmark DAC1~

[windwalker]

yes , 的確就是SRC....
SRC不見得是壞事....不用視之為畏途....

[狂人]

重新貼一下之前因資料庫問題而遺失的留言。純屬記憶中的資料，如有殘缺錯誤等等請各位提醒，感謝。

前幾天去逛 Analog Device 上面查 DAC 與 OP 的資料之時，發現了一篇有點年齡的文章，敘述使用某種數位介面與專屬之數位接收與取樣率轉換的手段來杜絕 Jitter 的影響。看起來好像很有趣，所以就翻了下去，越看越覺得有些講法好像之前在那邊看過，看到最後終於瞭解了，基本上這個就是 Benchmark 拿來稱之為 ultralock 的東西啊，只是輸入介面變成數種可選擇的介面，而當時該專屬數位接收與取樣轉換晶片尚未公開。

這個的作法是以非整數的倍率提昇取樣率，所以取樣率轉換器的運算式相當重要，而就算是計算試優良也會對聲音本體造成影響，不一定會往好的方向走。

這....這不就是傳說中的SRC嗎？

計算能力強大，計算式精密精準的SRC並非是個不好的東西。所以也不一定差。

[Zulu]

http://www.rme-audio.com/english/techinfo/steadyclock.htm

RME這個SteadyClock技術似乎也是同一個原理。而且這個技術應該已經晶片化了。

Usually a clock section consists of an analog PLL for external synchronization and several quartz oscillators for internal synchronisation. SteadyClock requires only one quartz, using a frequency not equalling digital audio, therefore effectively avoiding disturbances. Latest circuit designs like hi-speed digital synthesizer operating at unsurpassed 200 MHz, a fully digital PLL design, and efficient analog filtering allow RME to realize a completely newly developed clock technology, right within the FPGA, at lowest costs. The clock's performance exceeds even professional expectations. Despite its remarkable features, SteadyClock reacts quite fast compared to other techniques. It locks in fractions of a second to the input signal, follows even extreme varipitch changes with phase accuracy, and locks directly within a range of 28 kHz up to 200 kHz.

Compared to other technologies, one of SteadyClock's main advantages is its single stage design. Usually the PLL consists of a first stage reacting as broad clock locking circuit, then a second stage acts as narrow locking circuit. Only the narrow circuit provides jitter suppression, so that locking takes some time, and in varipitch applications, where the second stage does not get active at all, nearly no jitter suppression is provided. SteadyClock locks directly and provides high jitter suppression throughout!

[Zulu]

剛在CEC網站上看DA53的介紹中有一段好像是SRC，又好像不是de-jitter technique的話。

http://www.cec-web.co.jp/products/dac/da53_e.html

Input/output jacks
DA53 supports up to 48kHz input sampling frequency via USB, up to 24bit/96kHz via TOS LINK and up to 24bit/192kHz via SP/DIF COAX and AES/EBU. All of these input signals are upsampled with 24 bit/195kHz. By upsampling to 195kHz instead of 192kHz, it is possible for internal operation to avoid intermodulation with any incoming sample frequency. Analog output signals are always available from the both of balanced XLR and Unbalanced RCA, regardless of the input.